Digital electronic devices, such as digital computers, calculators, and other devices, perform arithmetic calculations on values in integer or “fixed point” format, in fractional or “floating point” format, or both. IEEE Standard 754 (hereinafter “IEEE Std. 754” or “the Standard”), published in 1985 by the Institute of Electrical and Electronic Engineers and adopted by the American National Standards Institute (ANSI), defines several standard formats for expressing values in floating point format and a number of aspects regarding behavior of computation in connection therewith. In accordance with IEEE Std. 754, a representation in floating point format comprises a plurality of binary digits, or “bits,” having the structuresemsb . . . elsbfmsb . . . flsb where bit “s” is a sign bit indicating whether the entire value is positive or negative, bits “emsb . . . elsb” comprise an exponent field that represents the exponent “e” in unsigned binary biased format, and bits “fmsb . . . flsb” comprise a fraction field that represents the fractional portion “f” in unsigned binary format (“msb” represents “most significant bit” and “lsb” represents “least significant bit”). The Standard defines two general formats, namely, a “single” format which comprises thirty-two bits, and a “double” format which comprises sixty-four bits. In the single format, there is one sign bit “s,” eight bits “e7 . . . e0” comprising the exponent field and twenty-three bits “f22 . . . f0” comprising the fraction field. In the double format, there is one sign bit “s,” eleven bits “e10 . . . e0” comprising the exponent field and fifty-two bits “f51 . . . f0” comprising the fraction field.
As indicated above, the exponent field of the floating point representation “emsb . . . elsb” represents the exponent “E” in biased format. The biased format provides a mechanism by which the sign of the exponent is implicitly indicated. In particular, the bits “emsb . . . elsb” represent a binary encoded value “e” such that “e=E+bias.” This allows the exponent E to extend from −126 to +127, in the eight-bit “single” format, and from −1022 to +1023 in the eleven-bit “double” format, and provides for relatively easy manipulation of the exponents in multiplication and division operations, in which the exponents are added and subtracted, respectively.
IEEE Std. 754 provides for several different formats with both the single and double formats which are generally based on the bit patterns of the bits “emsb . . . elsb” comprising the exponent field and the bits fmsb . . . flsb comprising the fraction field. If a number is represented such that all of the bits “emsb . . . elsb” of the exponent field are binary one's (i.e., if the bits represent a binary-encoded value of “255” in the single format or “2047” in the double format) and all of the bits fmsb . . . flsb of the fraction field are binary zeros, then the value of the number is positive or negative infinity, depending on the value of the sign bit “s”. In particular, the value “v” is ν=(−1)s∞, where “∞” represents the value of “infinity.” On the other hand, if all of the bits “emsb . . . elsb” of the exponent field are binary one's and if the bits fmsb . . . flsb of the fraction field are not all zero's, then the value that is represented is deemed “not a number,” abbreviated in the Standard by “NaN.”
If a number has an exponent field in which the bits “emsb . . . elsb” are neither all binary ones nor all binary zeros (i.e., if the bits represent a binary-encoded value between 1 and 254 in the single format or between 1 and 2046 in the double format), the number is said to be in a “normalized” format. For a number in the normalized format, the value represented by the number is ν=(−1)s2e-bias(1.|fmsb . . . flsb), where “|” represents a concatenation operation. Effectively, in the normalized format, there is an implicit most significant digit having the value “one,” so that the twenty-three digits in the fraction field of the single format, or the fifty-two digits in the fraction field of the double format, will effectively represent a value having twenty-four digits or fifty-three digits of precision, respectively, where the value is less than two, but not less than one.
On the other hand, if a number has an exponent field in which the bits “emsb . . . elsb” are all binary zeros, representing the binary-encoded value of “zero,” and a fraction field in which the bits fmsb . . . flsb are not all zero, the number is said to be in a “denormalized” format. For a number in the denormalized format, the value represented by the number is ν=(−1)s2e-bias+1(0.|fmsb . . . flsb). It will be appreciated that the range of values of numbers that can be expressed in the denormalized format is disjoint from the range of values of numbers that can be expressed in the normalized format, for both the single and double formats. Finally, if a number has an exponent field in which the bits “emsb . . . elsb” are all binary zeros, representing the binary-encoded value of “zero” and a fraction field in which the bits fmsb . . . flsb are all zero, the number has the value “zero” (reference format 30). It will be appreciated that the value “zero” may be positive zero or negative zero, depending on the value of the sign bit.
Generally, floating point units to perform computations whose results conform to IEEE Std. 754 are designed to generate a result in response to a floating point instruction in three steps:                (a) In the first step, an approximation calculation step, an approximation to the absolutely accurate mathematical result (assuming that the input operands represent the specific mathematical values as described by IEEE Std. 754) is calculated that is sufficiently precise. This allows the accurate mathematical result to be summarized by a sign bit, an exponent (typically represented using more bits than are used for an exponent in the standard floating point format), and some number “N” of bits of the presumed result fraction, plus a guard bit and a sticky bit. The value of the exponent will be such that the value of the fraction generated in step (a) consists of a “1” before the binary point and a fraction after the binary point. The bits are calculated so as to obtain the same result as the following conceptual procedure (which is impossible under some circumstances to carry out in practice): calculate the mathematical result to an infinite number of bits of precision in binary scientific notation, and in such a way that there is no bit position in the significand such that all bits of lesser significance are 1-bits (this restriction avoids the ambiguity between, for example, 1.100000 . . . and 1.011111 . . . as representations of the value “one-and-one-half”); then let the N most significant bits of the infinite significand be used as the intermediate result significand, let the next bit of the infinite significand be the guard bit, and let the sticky bit be “0” if and only if all remaining bits of the infinite significand are 0-bits (in other words, the sticky bit is the logical OR of all remaining bits of the infinite fraction after the guard bit).        (b) In the second step, a rounding step, the guard bit, the sticky bit, perhaps the sign bit, and perhaps some of the bits of the presumed significand generated in step (a) are used to decide whether to alter the result of step (a). For the rounding modes defined by IEEE Std. 754, this is a decision as to whether to increase the magnitude of the number represented by the presumed exponent and fraction generated in step (a). Increasing the magnitude of the number is done by adding “1” to the significand in its least significant bit position, as if the significand were a binary integer. It will be appreciated that, if the significand is all 1-bits, then magnitude of the number is “increased” by changing it to a high-order 1-bit followed by all 0-bits and adding “1” to the exponent.        
Regarding the rounding modes, it will be further appreciated that,                (i) if the result is a positive number, and                    (a) if the decision is made to increase, effectively the decision has been made to increase the value of the result, thereby rounding the result up (i.e., towards positive infinity), but            (b) if the decision is made not to increase, effectively the decision has been made to decrease the value of the result, thereby rounding the result down (i.e., towards negative infinity); and                        (ii) if the result is a negative number, and                    (a) if the decision is made to increase, effectively the decision has been made to decrease the value of the result, thereby rounding the result down, but            (b) if the decision is made not to increase, effectively the decision has been made to increase the value of the result, thereby rounding the result up.                        (c) In the third step, a packaging step, the result is packaged into a standard floating point format. This may involve substituting a special representation, such as the representation defined for infinity or NaN if an exceptional situation (such as overflow, underflow, or an invalid operation) was detected. Alternatively, this may involve removing the leading 1-bit (if any) of the fraction, because such leading 1-bits are implicit in the standard format. As another alternative, this may involve shifting the fraction in order to construct a denormalized number. As a specific example, it is assumed that this is the step that forces the result to be a NaN if any input operand is a NaN. In this step, the decision is also made as to whether the result should be an infinity. It will be appreciated that, if the result is to be a NaN or infinity, any result from step (b) will be discarded and instead the appropriate representation will be provided as the result.        
In addition, in the packaging step, floating point status information is generated, which is stored in a floating point status register. The floating point status information generated for a particular floating point operation includes indications, for example, as to whether                (i) a particular operand is invalid for the operation to be performed (“invalid operation”);        (ii) if the operation to be performed is division, the divisor is zero (“division-by-zero”);        (iii) an overflow occurred during the operation (“overflow”);        (iv) an underflow occurred during the operation (“underflow”); and        (v) the rounded result of the operation is not exact (“inexact”).        
These conditions are typically represented by flags that are stored in the floating point status register separate from the result itself. The floating point status information can be used to dynamically control the operations in response to certain instructions, such as conditional branch, conditional move, and conditional trap instructions that may be in the instruction stream subsequent to the floating point instruction. Also, the floating point status information may enable processing of a trap sequence, which will interrupt the normal flow of program execution. In addition, the floating point status information may be used to affect certain ones of the functional unit control signals that control the rounding mode. IEEE Std. 754 also provides for accumulating floating point status information from, for example, results generated for a series or plurality of floating point operations.
IEEE Std. 754 has brought relative harmony and stability to floating point computation and architectural design of floating point units. Moreover, its design was based on some important principles and rests on a sensible mathematical semantics that eases the job of programmers and numerical analysis. It also supports the implementation of interval arithmetic, which may prove to be preferable to simple scalar arithmetic for many tasks. Nevertheless, IEEE Std. 754 has some serious drawbacks, including:                (i) Modes (e.g., the rounding modes and traps enabled/disabled mode), flags (e.g., flags representing the status information stored in the floating point status register 25), and traps required to implement IEEE Std. 754 introduce implicit serialization issues. Implicit serialization is essentially the need for serial control of access (read/write) to and from globally used registers, such as the floating point status register 25. Under IEEE Std. 754, implicit serialization may arise between (1) different concurrent floating-point instructions and (2) between floating point instructions and the instructions that read and write the flags and modes. Furthermore, rounding modes may introduce implicit serialization because they are typically indicated as a global state, although in some microprocessor architectures, the rounding mode is encoded as part of the instruction operation code, which will alleviate this problem to that extent. Thus, the potential for implicit serialization makes the Standard difficult to implement coherently and efficiently in today's superscalar and parallel processing architectures without loss of performance.        (ii) The implicit side effects of a procedure that can change the flags or modes can make it very difficult for compilers to perform optimizations on floating point code. As a result, compilers for most languages must assume that every procedure call is an optimization barrier in order to be safe.        (iii) Global flags, such as those that signal certain modes, make it more difficult to do instruction scheduling where the best performance is provided by interleaving instructions of unrelated computations. Instructions from regions of code governed by different flag settings or different flag detection requirements cannot easily be interleaved when they must share a single set of global flag bits.        (iv) Furthermore, traps have been difficult to integrate efficiently into architectures and programming language designs for fine-grained control of algorithmic behavior.        
IEEE Std. 754 stores flag information as a global state and accumulates flag information from every operation, which makes it awkward and inefficient to accumulate flag status information from only a subset of executed operations, or to accumulate respective flag information separately and independently for a plurality of expressions, the execution of whose individual operations might be concurrent or interleaved in time.
In addition to the above drawbacks, existing computer architectures do not eliminate flags and trap enable bits as a global state, while supporting similar exception detection capabilities, even though existing computer architectures eliminate the rounding modes as a global state. This is typically done by statistically encoding the rounding mode as part of the instruction code. Examples of computer architectures that eliminate the rounding modes as a global state are demonstrated by the Digital Equipment Company ALPHA architecture, which partially eliminates the rounding modes, and Sun Microsystem's MAJC architecture, which completely eliminates the rounding modes.
Thus, there is a need for a system that avoids such problems when performing floating point operations and, in particular, when accumulating status information related to floating point operands.